Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One prior art non-volatile memory cell 10 is shown in FIG. 1. The split gate SuperFlash (SF) memory cell 10 comprises a semiconductor substrate 1 of a first conductivity type, such as P type. The substrate 1 has a surface on which there is formed a first region 2 (also known as the source line SL) of a second conductivity type, such as N type. A second region 3 (also known as the drain line) also of a second conductivity type, such as N type, is formed on the surface of the substrate 1. Between the first region 2 and the second region 3 is a channel region 4. A bit line (BL) 9 is connected to the second region 3. A word line (WL) 8 (also referred to as the select gate) is positioned above a first portion of the channel region 4 and is insulated therefrom. The word line 8 has little or no overlap with the second region 3. A floating gate (FG) 5 is over another portion of the channel region 4. The floating gate 5 is insulated therefrom, and is adjacent to the word line 8. The floating gate 5 is also adjacent to the first region 2. A coupling gate (CG) 7 (also known as control gate) is over the floating gate 5 and is insulated therefrom. An erase gate (EG) 6 is over the first region 2 and is adjacent to the floating gate 5 and the coupling gate 7 and is insulated therefrom. The erase gate 6 is also insulated from the first region 2.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate EG 6 with other terminals equal to zero volt. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state. Another embodiment for erase is by a applying a positive voltage Vegp on the erase gate EG 6, a negative voltage Vcgn on the coupling gate CG 7, and others terminal equal to zero volts. The negative voltage Vcgn couples negatively the floating gate FG 5, hence less positive voltage Vcgp is required for erasing. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition (cell state ‘1’). Alternately the wordline WL 8 (Vwle) and the source line SL 2 (Vsle) can be negative to further reduce the positive voltage on the erase gate FG 5 needed for erase. The magnitude of negative voltage Vwle and Vsle in this case is small enough not to forward the p/n junction. The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate CG 7, a high voltage on the source line SL 2, a medium voltage on the erase gate EG 6, and a programming current on the bit line BL 9. A portion of electrons flowing across the gap between the word line WL 8 and the floating gate FG 5 acquire enough energy to inject into the floating gate FG 5 causing the floating gate FG 5 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as ‘0’ state.
The cell 10 can be inhibited in programming (if, for instance, another cell in its row is to be programmed but cell 10 is to not be programmed) by applying an inhibit voltage on the bit line BL 9. The cell 10 is more particularly described in U.S. Pat. No. 7,868,375, whose disclosure is incorporated herein by reference in its entirety.
Exemplary operating voltages for the prior art design of FIG. 1 is shown below in
TABLE 1OperationWLCGFGBLSLReadVwlrdVcgrdVegrdVblrd0VProgramVwlpVcgpVegpIprog or VinhVslpErase0V/Vwle0V/VcgeVege0V0V/VsleStandby0V0V or Vcgrd0V or Vegrd0V0V
Typical values for the values listed in Table 1 are shown in Table 2:
TABLE 2Voltage LabelVoltageVwlrd~1-2 VVcgrd~1-2 VVegrd~1-2 VVblrd~0.2-1 VVwlp~0.5-1 VVcgp~9-10 VVegp~4-5 VIprog~0.2-2 μAVslp ~4-5 VVinh~2 VVege~7-11.5 VVcge ~−7 to −9 VVegp ~7 to 9 VVwle ~−0.4 VVsle ~−0.4 V
FIG. 2 depicts a typical prior art architecture for a two-dimensional prior art flash memory system. Die 12 comprises: memory array 15 and memory array 20 for storing data, the memory array optionally utilizing memory cell 10 as in FIG. 1; pad 35 and pad 80 for enabling electrical communication between the other components of die 12 and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip; high voltage circuit 75 used to provide positive and negative voltage supplies for the system; control logic 70 for providing various control functions, such as redundancy and built-in self-testing; analog logic 65; sensing circuits 60 and 61 used to read data from memory array 15 and memory array 20, respectively; row decoder circuit 45 and row decoder circuit 46 used to access the row in memory array 15 and memory array 20, respectively, to be read from or written to; column decoder 55 and column decoder 56 used to access the column in memory array 15 and memory array 20, respectively, to be read from or written to; charge pump circuit 50 and charge pump circuit 51, used to provide increased voltages for program and erase operations for memory array 15 and memory array 20, respectively; high voltage driver circuit 30 shared by memory array 15 and memory array 20 for read and write (erase/program) operations; high voltage driver circuit 25 used by memory array 15 during read and write operations and high voltage driver circuit 26 used by memory array 20 during read and write (erase/program) operations; and bitline inhibit voltage circuit 40 and bitline inhibit voltage circuit 41 used to un-select bitlines that are not intended to be programmed during a write operation for memory array 15 and memory array 20, respectively. These functional blocks are understood by those of ordinary skill in the art, and the block layout shown in FIG. 2 is known in the prior art.
As can be seen from the foregoing, charge pumps play an important role in the operation of flash memory devices. High voltages are required for the program and erase functions.
FIG. 3 depicts prior art charge pumps. During a program operation, SL pump 100 is used to generate the Vslp and Vegp voltages (which are typically around 4V to 5V), and CG-EG pump 110 is used to generate the Vcgp voltage (which is typically around 9V to 10V). During an erase operation, SL pump 100 is not used, and CG-EG pump is used to generate the Vege voltage (which is typically around 10 to 11.5V). These voltages are relatively high voltages that consume significant levels of power.
What is needed are improved charge pumps that can generate voltages for the program and erase operations in flash memory devices that are lower voltages than those used in prior art charge pumps.